Fpga / sopc learning development kit altera cyclone lcd

Fpga / sopc learning development kit altera cyclone lcd

FPGA / SOPC Learning Development Kit ALTERA CYCLONE LCD
We uphold the concept of the practical everywhere intentions for the sake of users, version 2.0, on the basis of careful re-creation of each function are examples of well-designed practical procedures, and to prepare detailed tutorials, whether or developed for learning prototype, a very practical significance. In addition, we include the Cyclone Design, such as Cyclone II several core board for users to choose, and constantly develop and supply a range of practical functions expansion boards, extended performance. Whether learning, development, the kit is your right choice.
* Cyclone core: EP1C12Q240C8, EP1C6Q240C8
* CycloneII core: EP2C8Q208C8, EP2C5Q208C8, EP2C20Q208C8
* Flash: 2Mbyte or 8 Mbyte (EP2C20 only), (pre-configuration of 2 M byte sufficient to meet most needs. Designed to support four M Byte, if special needs, users may need to change their own 4 M byte, such as AM29LV320)
* EPCS1 or EPCS4 chip configuration: EP1C6 and EP2C5 core board with EPCS1; EP1C12 and EP2C8 and EP2C20 with EPCS4 core board
* Provides configuration modes: JTAG and AS. In addition pin configuration leads through the pin, allowing users to design future CPLD + Flash configuration mode;
* All IO, Avalon bus, and so on through the 4-pin configuration row of pins leads, users can play full freedom, the expansion of more flexible
* RS-232 serial port: for the computer and data communication
* VGA Interface: direct VGA display with docking with FPGA Implementation of the agreement VGA interface can be displayed on monitors in the text, pattern, etc.
* PS / 2 mouse, keyboard interface: standard mouse, keyboard interface, the routine use of VHDL and at the same time in the digital display and keyboard scan code ASCII code, can also be combined to SOPC programming on the LCD display
* 16 * 2 character LCD interface: English characters and can display custom characters
* 128 * 64 graphical LCD interface : can display Fonts, graphics, etc.
* Buzzer: Use NIOSS II timer interrupt programming produced specific waveform can play all kinds of music
(1) using USB-UART bridge chip CP2102, and USB2.0 compatible with USB1.1 agreement, the maximum communication speed of 1 Mbps, can be used directly in communication rate is not very high demands of the occasion, such as industrial control equipment, instrumentation, convenience practical; developers need not know how to design USB protocol and drivers, as the only similar serial communications can operate, thus making the development cycle short, low-risk, low-cost addition, the small size of its anti-jamming performance, and stable and reliable work, the normal operating temperature range: -40 to +85 ?. With the CD-ROM package, with the chip data manual, drivers, as well as examples of procedures.
(2) Experimental USB1.1 interface directly to the expansion of FPGA IO USB interface for assessment FPGA USB Controler achieve the functions of HDL used in FPGA Although the realization of a USB controller is feasible, but in fact achieve up is not an easy thing, and its occupation of FPGA resources and not worth In total, speaking from a certain angle, the more unrealistic for the product.
* Digital paragraph 4 of 7: provide NiosII with VHDL and dynamic scanning procedures, using VHDL for automatic dynamic scanning, off-CPU processing time
* Four keys Switches: uphold the same simple style, not pursuing, but for simplicity, savings limited IO resources for NiosII external keystrokes, such as interruption experimental enough.
FPGA / SOPC Learning Development Kit main board