74HC273D / 74HC273 / octal d-type flip-flop with reset

74HC273D / 74HC273 / octal d-type flip-flop with reset

Now over 1,500 items in our Store!
Octal D-type flip-flop with reset; positive-edge trigger
Ideal buffer for MOS microprocessor or memory
Eight positive edge-triggered D-type flip-flops
See "377" for clock enable version
See "373" for transparent latch version
The 74HC/HCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Q
All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements.
And we salute our friends in other countries around the world!